Electromagnetic Compatibility for Electric Vehicles

CISPR-25 RF emissions ambient test pitfalls

CISPR-25 is not very specific about device under test and support equipment configuration during chamber ambient test. The automotive OEM require the ambient for RE, CE-V, CE-I with support equipment energized. The test laboratories will typically disconnect VBATT line from LISN output. The GND line remains connected to LISN. By doing so is assumed that DUT is not energized. The support equipment remains connected to the input of the LISNs being turned on (energized). The CAN bus is powered but w/o traffic. It is unclear if the load simulator energized it means powered but inactive (standby). By activating PWM pulses as inputs for DUT it may yield unwanted CE-I and RE ambient noise. All these aspects must be clarified in the EMC test plan.

In the sample presented the CE-V ambient noise is well below the 6 dB requirement. However, this type of noise is being captured while DUT's integrated buttons are being pressed and released via a pneumatic system with no electrical connection to DUT or test ground plane. Specifying that DUT must be unpowered may not be enough, the DUT's buttons should not be mechanically activated, nor its inputs subjected to electrical signals.

Christian Rosu

RI 115 copy and paste fake report

The automotive OEM that certifies EMC laboratories to carry out validation testing invested a lot of trust in accuracy and correctness of so called "sign-off" reports. This "sign-off test results"  or "not for sign-off test results" statement maybe an excuse for skipping a full review if the summary looks clean.

The automotive electronic device supplier must always verify in detail the report to clarify each reported non-conformance. Otherwise it may adversely affect the entire validation process through endless testing to fix potential false issues.

The sample of bad report shown below may easily go undetected by those searching for easy resolutions (pass / fail). 

Page #6 vs Page #18

In tis particular case two samples (7000 & 7002) are being evaluated for near filed interferences from portable transmitters.

The requirement for DUT in question is to pass Level 1 in band#9 (no deviation allowed under 7 Watts). The testing is carried out at 14 Watts, which is the Level 2 Severity. Whenever a deviation occurs the test operator must threshold the lowest severity level where the problem goes away.

The issue with the above result is that the same severity level threshold result was copied from one sample to another (7002 to 7000). It is impossible to have identical 3-digit accuracy readings between two test samples for the same antenna position and orientation. In fact, considering the uncertainty of test equipment combined with HW/SW tolerances of DUT it is impossible if scanning the same sample twice. The test result data file is generated automatically by the software running the test equipment. Chances to be a copy and paste mistake are zero.
Page #7 vs Page #24

Looking over page's date/time the scan below was generated before the scan above. However the order of pages is as was listed in the full report.

Page #9 vs Page #21
The test operator was in rush missing to change the test sample number from 7002 to 7000. Page #9 was supposed to show results from sample #7000. For the failed frequency step (850 MHz) the test operator slightly changed the Level 1 threshold value on the second tested sample (from 6.058 to 6.15 Watts) leaving unchanged the level 2 threshold values for all other  frequencies. Looking closely to date/time stamps they also are identical on both pages. Is this a honest mistake? 

This kind of precision in measurements would humiliate any theory so far.

Page #11 vs Page #23

The perfect DUT type ever, perfect RI 115 equipment, perfect test operator, perfect identical hand portable transmitters immunity!

Going over pages's date/time they both have the same stamp. Theb why inserting them such that they apear to belong to separate test samples?

Page #12 vs Page #19

Surprisingly, but there is an antenna position where the result was either correctly tested or correctly represented.

This was the only instance where the RI 115 result from one sample was not copied over the for the other sample.

Page #13 vs Page #25

The RI 115 make up report saga continues. As long as the customer is preoccupied by the deviation in Level 1 it will never pay attention that only one sample was fully tested. The really bad part is that the designer will believe there is some sort of stability in DUT's behavior when in fact it was a huge instability.

Again same date/time stamp but different test sample numbers. How was this possible?

Christian Rosu

Trialon EMC Laboratory, Burton, MI

Igor Klivak

EMC-CS-2009.1 CI 210 (Us Vp-p calibration issue)

ES-XW7T-1A278-AC Immunity from Continuous Disturbances: CI 210

This test refers to continuous disturbances produced by vehicle’s charging system that can affect DUT functions.

FMC1278 Rev2 vs EMC-CS-2009.1 - CI 210 Requirements

  • Level 2 requirements, as delineated in ES-XW7T-1A278-AC was removed in EMC-CS-2009.1, then added back in FMC1278.
  • The frequency range allocated for severity levels was changed subsequently in all three Ford EMC specifications.
  • The most significant differences for Us Vp-p requirements occurred between  ES-XW7T-1A278-AC & EMC-CS-2009.1.

CI 210 Frequency Steps

The most significant differences in frequency steps requirements occurred between  ES-XW7T-1A278-AC & EMC-CS-2009.1.

ES-XW7T-1A278-AC CI 210: Test Setup
  • The test harness connecting the DUT to the Test Fixture and transient pulse generator shall be < 2000 mm in length.
  • The DUT and wire harness shall be placed on an insulated support 50 mm above the ground plane. If the outer case of the DUT is metal and can be grounded when installed in the vehicle, the DUT shall be mounted and electrically connected to the ground plane.

ES-XW7T-1A278-AC CI 210: Test Procedure

  1. Adjust DC offset of the signal generator/audio amplifier to 13.5 volts with the DUT disconnected (open circuit)
  2. At each test frequency set and record the signal generator output to the specified voltage level with the DUT disconnected (open circuit).
  3. Without the test signal present, connect the DUT and verify that it is functioning correctly.
  4. Apply the test signal to the DUT and the Test Fixture such that all power and control circuits are exposed to the disturbance. All power and control circuits are tested simultaneously.
EMC-CS-2009.1 CI 210: Test Setup

  • The test harness connecting the DUT to the Load Simulator and modulated DC supply shall be < 2000 mm in length.
  • All DUT power/power return circuits shall be connected together at the modulated power supply.
  • Per previous versions of this requirement, a ground plane may be placed under the DUT and Load Simulator, but if used, the DUT and wire harness shall be placed on an insulated support 50mm above the ground  plane. Additionally, the negative connection of the modulated DC supply and case of the Load Simulator shall be referenced to the ground plane.

EMC-CS-2009.1 CI 210: Test Procedure

  1. Without the DUT connected, adjust the DC voltage offset "Up" of the modulated power supply to 13.5 volts. Initially set the AC voltage amplitude "Us" to zero volts.
  2. Connect and activate the DUT and verify it is functioning correctly. Verify that Up remains at 13.5 VDC. Adjust the supply as required to achieve this voltage level.
  3. At each test frequency increase Us to the corresponding stress level while the DUT is operating. The dwell time shall be at least 2 seconds. A longer dwell time may be necessary if DUT function response times are expected to be longer. This information shall be documented in the EMC test plan.
FMC1278 CI 210: Test Setup

  • The test harness connecting the DUT to the Load Simulator and modulated DC supply shall be < 2000 mm in length.
  • All DUT power/power return circuits shall be connected together at the modulated power supply.

FMC1278 CI 210: Test Procedure

  1. Without the DUT connected, adjust the DC voltage offset "Up" of the modulated power supply to DUT’s system voltage (13.5, 27 volts). “Us” is initially set to zero volts.
  2. At each test frequency adjust and record the signal generator output required to achieve the specified modulation voltage level “Us” with the DUT disconnected (open circuit). Use the frequency steps listed.
  3. Without the modulation signal present (i.e. Us = 0 volts), connect the DUT and verify it is functioning correctly.
  4. At each test frequency, apply the signal generator levels recorded in step (2) to the DUT and the Load Simulator such that all power and control circuits are exposed to the disturbance. The dwell time shall be at least 2 seconds. A longer dwell time may be necessary if DUT function response times are expected to be longer. This information shall be documented in the EMC test plan and test report.
Fixing EMC-CS-2009.1 CI 210 Us (Vp-p) calibration issue:

CI 210 test waveform is not the superimposed alternating voltage per ISO 16750-2. 
Prior to test Us is calibrated (substitution method) to maintain the required Us V(p-p) while DUT is driving high current loads (e.g. 30A): at each test frequency increase Us to the corresponding stress level while the DUT is operating. The amplifier (e.g. Techron 7796) is configured to operate as Voltage-Controlled Source. Whenever functions are paused between activations (very low current) the amplifier will increase its output voltage in an attempt to drive the requested current into DUT as recorded during Us (Vp-p) calibration. This will result in high voltage (e.g. above 40V) being present for long enough time at DUT VBATT input that can damage components.

The solution is to run CI 210 per FMC1278 that has corrected the test procedure: at each test frequency adjust and record the signal generator output required to achieve the specified modulation voltage level “Us” with the DUT disconnected (open circuit).

Christin Rosu

Shielding Effectiveness

The generic shielding effectiveness requirement is 40 dB for magnetic field, electric field, and plane waves. Depending on the application the frequency range can start from 10 Hz going up to GHz.

To predict shielding effectiveness (SE) of a metal sheet the following factors are summed:  Absorption Loss (A), Reflection Loss (R), re-Reflection Correction Factor (C).  SE = A + R – C (see MIL-HDBK-419A).

Absorption loss depends on material thickness, permeability, electrical conductivity, and the frequency of the incident wave.  It is the same for all electromagnetic waves.

Reflection loss depends on the distance of the EMI source to the material (different for electric, magnetic, and plane waves), material electrical conductivity, and the frequency of the incident wave.

Christian Rosu

Automotive BCI Test Limits

The Bulk Current Injection (BCI) test method simulates a field-to-wire coupling from nearby low frequencies radiated fields induced onto a test harness small relative to wavelength.
The coupling from BCI probe will increase with test frequency when the cable is electrically short, and then flatten out when the cable approaches and exceeds a half-wavelength in length.

The transducers (RF current transformers) inject current into both sides of the test harness, therefore both DUT and Load Simulator are subject to test. RF radiation from load simulator cables is possible, but it can be reduced placing 20cm of clip-on split-ferrite RF suppressers close to the transducer.

The BCI common-mode current injected in the test harness simulates an illuminating RF field.
To simulate conducted differential-mode disturbances the BCI induced current is injected in individul conductors.

Using the Substitution Method the actual current injected in test cables can vary from what was initially  calibrated, being less likely to over-test but more real-life representative.

To ensure the repeatability of test results, the cable under test must be centered within BCI current probe, the test set-up must be consistent, especially cable routing, placement of the clamp, and proximity to metal structures.

BCI Calibration Levels per MIL STD 416F CS114:

BCI Probe Insertion Loss per MIL STD 416F CS114:

RF Immunity Ratio mA versus V/m per MIL STD 416F:

Ford RI 112 (BCI) Calibration Limits requirements per FMC1278:

CAN Bus Off Recovery

CAN Bus Off is an error state of the CAN controller and it can be set only by the Transmitter Node when Transmit Error Counter is above 255. Such critical error is usually the result of a critical hardware issue (e.g. high level of electromagnetic field, bus wiring short-circuit, defective transceiver).

Methods to self-recover from a Node CAN Bus Off state:

1) Automatically after the CAN controller generates an interrupt.

2) Manually upon User request (ISO11898-1 §6.15).

In both the above  instances the bus turns back on after 128 occurrences of 11 consecutive Recessive Bits (BOSCH CAN 2.0B §8.12).

Auto-Bus-ON is not required by ISO 11989, therefore the CAN controller makers let the application to decide on its implementation. The automotive industry does not encourage the auto-bus-on feature.

If application's driver reports repeatedly the CAN Bus Off state the application should stop using the CAN.

Christian Rosu

CAN BUS Off Error Handling

CAN Bus Error Handling

Error handling is built into in the CAN protocol. Each node maintains two error counters: the Transmit Error Counter and the Receive Error Counter. Using the error counters, a CAN node can not only detect faults but also perform Error Confinement.


CAN Bus Error Detection Mechanisms

1. Bit Monitoring.

2. Bit Stuffing.

3. Frame Check.

4. Acknowledgement Check.

5. Cyclic Redundancy Check.


CAN Bus Error Confinement


The CAN bus is capable to distinguish between temporary erratic errors and continual erratic errors.

A node starts out in Error Active mode. When any one of the two Error Counters raises above

127, the node will enter a state known as Error Passive and when the Transmit Error Counter raises above 255, the node will enter the Bus Off state.


Error Active              node will transmit Active Error Flags when it detects errors.

Error Passive            node will transmit Passive Error Flags when it detects errors.

Bus Off                      node is disabled from transmit/receive operations.


Transmit errors give 8 error points

Receive errors give 1 error point


Correctly transmitted and/or received messages causes the counter(s) to decrease.


Whenever a node tries to transmit a message, if for whatever reason fails it will increases its Transmit Error Counter by 8 and transmits an Active Error Flag. Then it will attempt to retransmit the message, and if it fails will increment by 8 points the Transmit counter. Above 127 (i.e. after 16 attempts), this node goes Error Passive and from this moment it will transmit Passive Error Flags on the bus. A Passive Error Flag will not affect other bus traffic, the other nodes won’t hear the faulty node complaining about bus errors. However, the faulty node continues to increase its Transmit Error Counter and once above 255 it will go into Bus Off.


Error state of a node unit

Transmit error counter (TEC)

Receive error counter (REC)

Error active state

0 – 127


0 – 127

Error passive state




Bus off state

Minimum 256


For every active error flag that transmitted by a faulty node, the other nodes will increase their Receive Error Counters by 1. By the time that a faulty node goes Bus Off, the other nodes will have their Receive Error Counters below Error Passive limit (127). This count will decrease by one for every correctly received message the faulty node being in Bus off state.




Transmit/receive error counter change conditions

Transmit error counter (TEC)

Receive error counter (REC)


When the receive unit has detected an error, except when the receive unit detected a bit error while it was sending an active-error flag or overload flag.





When the receive unit has detected a dominant level in the first bit that it received after sending an error flag.





When the transmit unit has transmitted an error flag 1)



When the transmit unit has detected a bit error while sending an active-error flag or overload flag





When the receive unit has detected a bit error while sending an active-error flag or overload flag





When any unit has detected a dominant level in 14 consecutive bits from the beginning of an active-error or an overload flag, and each time the unit has detected a dominant level in 8 consecutive bits thereafter.


For a transmit unit



For a receive unit



When any unit has detected a dominant level in additional 8 consecutive bits after a passive-error flag, and each time the unit has detected a dominant level in 8 consecutive bits thereafter.


For a transmit unit



For a receive unit



When the transmit unit has transmitted a message normally (ACK returned and no errors detected until completion of EOF).


±0 when TEC = 0



When the receive unit has received a message normally (no errors detected until ACK slot and the unit was able to return ACK normally).



–1 when 1 REC 127

±0 when REC = 0

When REC > 127, a value between 119 to 127 is set in REC


When  the  unit  in  a  bus-off  state  has  detected  a  recessive  level  in  11 consecutive bits 128 times.

Cleared to TEC = 0

Cleared to REC = 0


1) The transmit error counter does not change in the following cases:

  •  When the transmit unit while in an error-passive state has detected an ACK error for reasons that ACK was not detected and has detected no dominant levels while sending a passive-error flag.
  • When the transmit unit has encountered a stuffing error during arbitration (dominant level is detected although it transmitted a recessive level as bit stuffing).


CAN Bus Failure Modes (ISO 11898)


1. CAN_H interrupted (a)

2. CAN_L Interrupted (a)

3. CAN_H shorted to battery voltage (a)

4. CAN_L shorted to ground (a)

5. CAN_H shorted to ground (a)

6. CAN_L shorted to battery voltage (a)

7. CAN_L shorted to CAN_H wire (b)

8. CAN_H and CAN_L interrupted at the same location (c)

9. Loss of connection to termination network (a)


Expected behavior:

  • a)     bus survives with a reduced S/N ratio
  • b)     bus survives with a reduced S/N ratio (optional)
  • c)     the resulting subsystem survives


Whenever a CAN Tx error count reaches 255, a node will turn bus off and potentially reset itself. A good implementation will not continue resetting a node if the problem persists. In addition to this safety mechanism, ECU's (electric control units) evaluates the duration between valid transmissions of the messages they expect to receive. Therefore, if the engine controller goes offline, nearly every ECU in the vehicle will report "Lost Communication with the Engine Controller." Typically, these type of CAN problems are identified by DTC's (diagnostic trouble codes). Depending on the severity of the issue, the vehicle might enter a "limp home" mode, or might be totally disabled. Limp-home mode is the condition when all the ECUs fail in the car network. A set of default parameters are initialized and your car can continue running only for some time before it is properly serviced by the OEM.


A CAN bus node (ECU) automatically goes bus on after 128 x 11 bits, which is the equivalent for 128 messages.

The 11 bits is the recessive time between messages so even in a 100% loaded bus, a bus off node will go bus on again.


Accordingly with ISO 11898, “a node can start the recovery from «bus-off» state only upon a user request”; it can be the ECU software or the CAN bus controller, to avoid a complete soft CPU reset. The ability to select between auto-recovery and manual recovery is CAN bus controller implementation defendant.


Scenario: Rx channel is damaged on Node 1 and rejects messages from Node 2. As result Node 2 will go buss off, then it auto-recovers, then immediately Node 1 reject messages collapsing the whole communication. The automotive industry does not encourages the auto-bus-on feature.



Baud rate


Application field

SAE J1939-11


Two-wire shielded twisted pair

Truck, bus

SAE J1939-12


Two-wire shielded twisted pair 12 V supply

Agricultural machine

SAE J2284


Two-wire twisted pair (non-shielded)


(high-speed: power train system)

SAE J2411

33.3k, 83.3k


Automobile (low-speed: body system)


62.5k, 125k, 250k, 500k,1M

Two-wire shielded twisted pair Power supply



125 k, 250 k, 500 k

Two-wire shielded twisted pair 24 V supply

Industrial equipment


10k, 20k, 25k, 50k, 125k

250k, 500k, 800k, 1M

Two-wire twisted pair

Optional (shielded, power supply)

Industrial equipment


125k, 250k, 500k, 1M

Two-wire shielded twisted pair Optional (power supply)

Industrial equipment



Communication speed

Purpose of use

Application range


Other protocols

Class A

Up to 10 kbps

(body system)

Lamp and light

Power window

Door lock

Power sheet

Keyless entry, etc.








Each carmaker’s

original protocol


Class B

10 kbps to 125 kbps

(status information system)

Electronic meter

Drive information

Auto air-conditioner

Failure diagnosis, etc.



Class C

125 kbps to 1 Mbps

(real time control system)

Engine control

Transmission control

Brake control

Suspension control, etc.


Class D

5 Mbps and over (multimedia)

Car navi,


by-Wire, etc.


D2B optical


IEEE 1394


Christian Rosu

How to reduce RF Emissions

Partitioning separates the system into critical and non-critical sections from EMC point of view.

Long I/O and power cables usually act as good antennas, picking up noise from the outside world and conducting this into the system. For unshielded systems, long PCB tracks may also act as antennas. Once inside the system, the noise may be coupled into other, more sensitive signal lines. It is therefore vital that the amount of RF energy allowed into the system be kept as low as possible, even if the input lines themselves are not connected to any sensitive circuit. This can be done by adding one or more of the following:

  • Series inductors or ferrite beads will reduce the amount of HF noise that reaches the microcontroller pin. They will have high impedance for HF, while having low impedance for low-frequency signals.

  • Decoupling capacitors on the input lines will short the HF noise to ground. The capacitors should have low ESR (equivalent series resistance). This is more important than high capacitance values. In combination with resistors or inductors, the capacitors will form low-pass filters. If the system is shielded, the capacitors should be connected directly to the shield. This will prevent the noise from entering the system at all. Special feed-through capacitors are designed for this purpose, but these may be expensive.

  • Special EMC filters combining inductors and capacitors in the same package are now delivered from many manufacturers in many different shapes and component values.


    Ferrites with high insertion loss are applied in a wide frequency range. Common mode interferences are filtered with ferrite sleeves and differential mode interferences with ferrite beads. The ferrite beads have the disadvantage that they absorb also the information signal. In order to prevent this, there are ferrites with special frequency dependent impedance.

    Current-compensated chokes are a special form of ferrite sleeves with more than a half turn. They have a large asymmetrical effective inductance, typically some mH, and a very small symmetrical inductance, also leakage inductance. The sum of all currents in this chokes should be zero. A small imbalance will cause the inductor partly going into saturation, which results in a decrease of effective inductance.

    Using ferrite sleeves to lower any currents flowing on the cable shields:



    Emissions: The most critical circuits for EMI emissions are the highly repetitive circuits, such as clocks, address enables, and high speed data busses. Even signals with low repetition rates, such as address bit 0, can cause problems with sensitive automotive radio receivers. Consider adding a ferrite bead or small resistor (10±33 ohms) in series with any clock or other high speed output, right at the driving pin. This will help damp any ringing, and also helps provide an impedance match.

    Always use the slowest logic family that will do the job; don’t use fast logic when it is unnecessary.



    Susceptibility: The most critical circuits for EMI susceptibility are the reset, interrupt, and control lines. The entire system can be brought to a halt if one of these lines is corrupted by EMI. Even though these circuits may have slow (or even nonexistent) repetition rates, they are still vulnerable to transients and spikes which can result in false triggering. Use high frequency filtering, such as small capacitors (0.001 mf typical) and ferrite beads (or 100 ohm resistors) to protect these lines. These filtering components should be installed right at the input pins to the microcontroller.

    Be especially careful with the reset circuitry, particularly when using external devices for watchdogs or detecting power loss. Any false triggering of these external circuits can cause a false reset, so these external circuits must be protected against EMI as well. Once again, small capacitors and ferrite beads or resistors are very effective as filters against spikes and transients.

    Define the boundaries of the island to encompass all high speed circuitry (microcontroller, crystal, RAM, ROM, etc.). Fill this area with a ground plane.

    Isolate every signal entering or leaving the island with a T-filter (ferrite-capacitor or resistor-capacitor). The capacitors are connected to the ground plane through a short lead.

    Isolate every power and ground trace with a series ferrite bead. Decouple the power and ground with a 0.01 mF capacitor at the capacitor energy point.

    Any signal not starting or ending on Micro-Island must be routed around the island. Later in this application note, we'll share some test results of this technique.


  • Use local power decoupling of every integrated circuit on the board.

  •  For devices with multiple power and ground pins, each pair of pins should be decoupled. High frequency capacitors in the 0.01±0.1 mf range should be installed as close as possible to the device.

  • For multi-layer boards, run a short trace from the power pin to the capacitor, and then drop the other lead into the ground plane.

  • For two layer boards, ``fat'' traces (with a length to width ratio of 5:1 or less) should be used on both the power and ground sides of the capacitor to minimize inductance.

  • In both cases, keep the leads as short as possible.

  • Additional protection can be provided by inserting a ferrite in series with the VCC line to the microcontroller. This must be installed on the VCC side of the capacitor, not on the IC side. This small LC filter further isolates the VCC traces from current demands of the switched device. This technique is strongly recommended for two layer and Micro-Island designs; it's optional for multi-layer designs.

  • Use high frequency decoupling at the power entry points. In addition to the standard 1±10 mf ``bulk'' capacitors, add a 0.01±0.1 mf high frequency capacitor in parallel at the power entry point. Due to internal resonances, the bulk capacitors are useless at frequencies above about 1 MHz. The high frequency capacitors are there to intercept any high frequency energy that tries to sneak out the power interface. For more protection, series ferrites can also be added. Be sure to keep the leads short on the decoupling capacitors. The self-inductance of wires and traces is about 8 nH/cm (20 nH/inch), so even a few millimeters of wire length can defeat the decoupling at high frequencies due to the inductance. Figure 13 gives several examples of how lead inductance defeats the decoupling capacitor. Note that once you are above the resonant frequency, using a larger capacitor provides no additional benefits, as the inductive reactance prevails.

  • Add high frequency capacitors (0.001 mf typical) to the input and outputs of all on-board voltage regulators. This will protect these devices against high levels of RF energy (which can upset the feedback) and will also help suppress VHF parasitic oscillations from these devices. Keep the capacitors close to the devices, with very short leads.

  • Don't overlook the ground leads in the signal interface, as these can provide sneak paths for common mode currents into and out of the system. Add a small ferrite bead in the ground lead, to complete the filtering of the interface.

  • Use ferrite beads at power entry points. Beads are an inexpensive and convenient way to attenuate frequencies above 1 MHz without causing power loss at low frequencies. They are small and can generally be slipped over component leads or conductors.

  • Use multistage filtering to attenuate multiband power supply noise:


  • In high-speed digital circuits, the clock circuitry is usually the biggest generator of wide-band noise. In faster MCUs, these circuits can produce harmonic distortions up to 300 MHz, which should be eliminated. In digital circuits, the most vulnerable elements are the reset lines, interrupt lines, and control lines.

  • One of the most obvious, but often overlooked, ways to induce noise into a circuit is via a conductor. A wire run through a noisy environment can pick up noise and conduct it to another circuit, where it causes interference. The designer must either prevent the wire from picking up noise or remove noise by decoupling before it causes interference. The most common example is noise conducted into a circuit on the power supply leads. If the supply itself, or other circuits connected to the supply, are sources of interference, it becomes necessary to decouple before the power conductors enter the susceptible circuit. This type of coupling occurs when currents from two different circuits flow through a common impedance. The voltage drop across the impedance is influenced by both circuits.


  • Ground currents from both circuits flow through the common ground impedance. The ground potential of circuit 1 is modulated by ground current 2. A noise signal or a dc offset is coupled from circuit 2 to circuit 1 through the common ground impedance.


    Coupling through radiation, commonly called crosstalk, occurs when a current flowing through a conductor creates an electromagnetic field which induces a transient current in another nearby conductor.


    A ground plane is a useful tool to combat crosstalk. Crosstalk coupling between two tracks is mediated via inductive, capacitive and common ground impedance routes, usually a combination of all three.


    The two basic types of radiated emission are differential mode (DM) and common mode (CM).


    Common-mode radiation or monopole antenna radiation is caused by unintentional voltage drops that raise all the ground connections in a circuit above system ground potential. The electric field term for CM is: E = 4 (1) 10–7 (f L If/d) volts/meter


    f = frequency in Hz

    L = cable length in m

    d = distance from cable in m

    If = CM current in cable at frequency fA


    Common mode radiation which is due mainly to cables and large metallic structures increases at a rate linearly proportional to frequency (ignoring resonances). There are two factors which make common mode coupling the major source of radiated emissions:

  • cable radiation is much more effective than from a small loop, and so a smaller common mode current (of the order of microamps) is needed for the same field strength;

  • cable resonance usually falls within the range 30-100MHz, and radiation is enhanced over that of the short cable model.


    A great deal of interference propagates in common-mode, and this can be attenuated using common-mode (CM) ferrite chokes.

    Ferrite effectiveness increases with frequency. The impedance of a ferrite choke is typically around 50ohm at 30MHz, rising to hundreds of ohms above 100MHz (the actual value depends on shape, size and material composition). Usually a ferrite has little effect at frequencies lower than 30MHz, becomes most effective above 100MHz and falls off in performance as the frequency approaches 1GHz. A useful property of ferrites is that their impedance becomes resistive at the higher frequencies, so that interference energy tends to be absorbed rather than reflected.


    Differential-mode radiation occurs when an alternating current passes through a small loop. The magnitude of the radiation from the loop varies in proportion to the current. The electric field term for DM is: E = 265 (10–16 ) (A If f2/d) volts/meter


    A = loop area in m/2

    d = distance from loop center in m

    If = current at frequency A in Hz

    f = frequency (of harmonic) in Hz


    Due to the magnitude of the electric field, CM radiation is much more of an emission problem than DM radiation. To minimize CM radiation, common current must be reduced to zero by means of a sensible grounding scheme.

    Higher supply voltages mean greater voltage swings and more emissions. Lower supply voltages can affect susceptibility.

    Higher frequency yields more emissions. Periodic signals generate more emissions. High-frequency digital systems create current spikes when transistors are switched on and off. Analog systems create current spikes when load currents change.



    Nothing is more important to circuit design than a solid and complete power system. An overwhelming majority of all EMC problems, whether they are due to emissions, susceptibility, or self-compatibility, have inadequate grounding as a principal contributor. The most important EMC function of a ground system is to minimize interference voltages at critical points compared to the desired signal. To do this, it must present a low transfer impedance path at these critical locations.


    Interference voltages VN which are developed across the impedances can create emission or susceptibility problems. At high frequencies (above a few kHz) or high rates of change of current the impedance of any linear connection is primarily inductive and increases with frequency (V = - L · di/dt), hence ground noise increases in seriousness as the frequency rises.

    Interference current IN induced in, say, the output lead, flows through the ground system, passing through Z2 again and therefore inducing a voltage in series with the input, before exiting via stray capacitance to the mains supply connection. To deal with the problem ensure that the interfering currents are not allowed to flow through the sensitive part of the ground network.



     There are three types of signal grounding: single point, multipoint and hybrid:


    Grounding principles:

  • All conductors have a finite impedance which increases with frequency

  • Two physically separate ground points are not at the same potential unless no current flows between them

  • At high frequencies there is no such thing as a single point ground

    Grounding rules:

  • identify the circuits of high di/dt (for emissions) - clocks, bus buffers/drivers, high-power oscillators

  • identify sensitive circuits (for susceptibility) - low-level analogue, fast digital data

  • minimize their ground inductance by - minimizing the length and enclosed area implementing a ground plane keeping critical circuits away from the edge of the plane

  • ensure that internal and external ground noise cannot couple out of or into the system: incorporate a clean interface ground

  • partition the system to control common mode current flow between sections

  • create, maintain and enforce a ground map


    Ground layout is especially critical, ground returns from high-frequency digital circuits and low-level analog circuits must not be mixed.



     Proper printed circuit board (PCB) layout is essential to prevention of EMI.



    Power Decoupling

    When a logic gate switches, a transient current is produced on power supply lines. These transient currents must be damped and filtered out. High-frequency ceramic capacitors with low-inductance are ideal for this purpose.


    Transient currents from high di/dt sources cause ground and trace "bounce" voltages. The high di/dt generates a broad range of high frequency currents that excite structures and cables to radiate.

    A variation in current through a conductor with a certain inductance, L, results in a voltage drop of: V = L. di/dt

    The voltage drop can be minimized by reducing either the inductance or the variation in current over time. Three ways to prevent interference are:

    1. Suppress the emission at its source.

    2. Make the coupling path as inefficient as possible.

    3. Make the receptor less susceptible to emission.


    Device-Level Techniques

  • Use multiple power and ground pins

  • Use fewer clocks

  • Eliminate fights or race conditions

  • Reduce output buffer drive

  • Use low-power techniques

  • Reduce internal power/ground trace impedance

  • For long buses, keep high-speed traces separated from lowspeed traces. Add extra spacing between high-speed and lowspeed signals and run high-frequency signals next to a ground bus.

  • Supply good ground imaging for long traces, high-speed signals

  • Turn off clocks when not in use

  • Eliminate charge pumps if possible

  • Minimize loop area within chip


    Board-Level Techniques

  • Use ground and power planes

  • Maximize plane areas to provide low impedance for power supply decoupling

  • Minimize surface conductors

  • Use narrow traces (4 to 8 mils) to increase high-frequency damping and reduce capacitive coupling

  • Segment ground/power for digital, analog, receiver, transmitter,relays, etc.

  • Separate circuits on PCB according to frequency and type

  • Do not notch PCB; traces routed around notches can cause unwanted loops

  • Use multilayer boards to enclose traces between power and ground planes

  • Avoid large open-loop plane structures

  • Border PCB with chassis ground; this provides a formidable shield (or field interceptor) to prevent radiation (or reduce susceptibility) at the circuit boundaries.

  • Use multipoint grounding to keep ground impedance low at high frequencies

  • Use single-point grounding only for low-frequency, low-level circuits

  • Keep ground leads shorter than one-twentieth (1/20) of a wavelength to prevent radiation and to maintain low impedance

              Routing noise-reduction techniques

  • Use 45-degree, rather than 90-degree, trace turns. Ninety-degree turns add capacitance and cause change in the characteristic impedance of the transmission line.

  • Keep spacing between adjacent active traces greater than trace width to minimize crosstalk.

  • Keep clock signal loop areas as small as possible.

  • Keep high-speed lines and clock-signal conductors short and direct.

  • Do not run sensitive traces parallel to traces that carry highcurrent, fast-switching signals.

  • Eliminate floating digital inputs to prevent unnecessary switching and noise generation:

                    – Configure multipurpose device pins as outputs.

                    – Set three-state pins to high impedance.

                    – Use appropriate pull-up or pull-down circuitry.

  • Avoid running traces under crystals and other inherently noisy circuits.

  • Run corresponding power and ground and signal and return traces in parallel to cancel noise.

  • Keep clock traces, buses, and chip-enable lines separate from input/output (I/O) lines and connectors.

  • To protect critical traces:

                    – Use 4-mil to 8-mil traces to minimize inductance.

                    – Route close to ground plane.

                    – Sandwich between planes.

                    – Guard-band with a ground on each side.

  • Use orthogonal crossovers for traces and intersperse ground traces to minimize crosstalk, especially when analog and digital signals are routed together.

  • Route clock signals perpendicular to I/O signals.


    Filter techniques

  • Filter the power line and all signals entering a board.

  • Use high-frequency, low-inductance ceramic capacitors for integrated circuit (IC) decoupling at each power pin (0.1 μF for up to 15 MHz, 0.01 μF over 15 MHz).

  • Use tantalum electrolytic capacitors as bulk decoupling capacitors at headers and connectors. Bulk decoupling capacitors recharge the IC decoupling capacitors.

  • Bypass all power feed and reference voltage pins for analog circuits.

  • Bypass fast switching transistors.

  • Decouple locally whenever possible.

  • Decouple power/ground at device leads.

  • Use ferrite beads at power entry points. Beads are an inexpensive and convenient way to attenuate frequencies above 1 MHz without causing power loss at low frequencies. They are small and can generally be slipped over component leads or conductors.

  • Use multistage filtering to attenuate multiband power supply noise


    Other design techniques

  • Mount crystals flush to board and ground them.

  • Use shielding where appropriate.

  • Use the lowest frequency and slowest rise time clock that will do the job.

  • Use series termination to minimize resonance and transmission reflection. Impedance mismatch between load and line causes a portion of the signal to reflect. Reflections induce ringing and overshoot, producing significant EMI. Termination is needed when line length, L, (inches) exceeds 3 tr (ns). The value of the termination resistor is given by:RL = Z0/(1 + CL/CLine)1/2


    Z = Characteristic impedance of the line without the load(s)

    CL = Total load distributed along the line

    CLine = Total capacitance of the line without the load(s)

  • Route adjacent ground traces closer to signal traces than other signal traces for more effective interception of emerging fields.

  • Place properly decoupled line drivers and receivers as close as practical to the physical I/O interface. This reduces coupling to other PCB circuitry and lowers both radiation and susceptibility.

  • Shield and twist noisy leads together to cancel mutual coupling out of the PCB.

  • Use clamping diodes for relay coils and other inductive loads.

  • For emission diagnostics use clamp ferrites on harnesses to eliminate effect of conducted energy.


    Capacitors, inductors, and ferrites characteristically are used to filter narrow frequency bands.

    Ferrites are a ceramic material having very poor conductivity. Ferrites act as a combination inductor and frequency-dependent resistor whose resistance is proportional to frequency. For this reason ferrite beads are great for eliminating high-frequency noise on (low-current) power supplies and digital clock signals. Ferrite beads are used to provide high impedance at the frequencies of the unwanted noise.


    Digital circuit designers like to think of signals in terms of their voltage. Signal integrity and EMC engineers must think of signals in terms of their current.

    There are two things that every good circuit designer should know about signal currents.

    1. Signal currents always return to their source (i.e. current paths are always loops)

    2. Signal currents take the path(s) of least impedance.


    At megahertz frequencies and higher, signal current paths are relatively easy to identify. This is because the path of least impedance at high frequencies is generally the path of least inductance, which is generally the path that minimizes the loop area. Currents return as close as possible to the path of the outgoing current.


    At low frequencies (generally kHz frequencies and below), the path of least impedance tends to be the path(s) of least resistance. Low frequency currents are more difficult to trace, since they will spread out significant current return paths may be relatively distance from the outgoing current path.


    There are some situations where a well-placed gap in the return plane is called for. However, these are relatively rare and always involve a need to control the flow of low-frequency currents. The safest rule-of-thumb is to provide one solid plane for returning all signal currents. In situations where you expect that a particular low-frequency signal is susceptible or is capable of interfering with the circuitry on your board, use a trace on a separate layer to return that current to its source.


    In general, never split, gap or cut your board's signal return plane. If you are convinced that a gap is necessary to prevent a low-frequency coupling problem, seek advice from an expert. Don't rely on design guidelines or application notes and don't try to implement a scheme that "worked" in someone else's "similar" design.


    Many times simple board designs that should have had no trouble at all meeting EMC requirements at no additional cost or effort, wind up being heavily shielded and filtered because they violated this simple rule.


    Why is the location of connectors so important? At frequencies below a few hundred megahertz, wavelengths are on the order of a meter or longer. Any possible antennas on the printed circuit board itself tend to be electrically small and therefore inefficient. However, cables or other devices connected to a board can serve as relatively efficient antennas. Signal currents flowing on traces and returning through solid planes result in small voltage differences between any two points on the plane. These voltage differences are generally proportional to the current flowing in the plane. When all connectors are placed along one edge of a board, the voltage between them tends to be negligible. However, high-speed circuitry located between connectors can easily develop potential differences of a few millivolts or greater between the connectors. These voltages can drive currents onto attached cables causing a product to exceed radiated emissions requirements.


    A board operating with a clock speed of 100 MHz should never fail to meet a radiated emissions requirement at 2 GHz. A well-formed digital signal will have a significant amount of power in the lower harmonic frequencies, but not so much power in the upper harmonics. Power in the upper harmonic frequencies is best controlled by controlling the transition times in digital signals. Longer transition times are preferred for EMC. Excessively long transition times can cause signal integrity and thermal problems. An engineering compromise must be reached between these competing requirements. A transition time that is approximately 20% of a bit period result in a reasonably good-looking waveform, while minimizing problems due to crosstalk and radiated emissions. Depending on the application, transitions times may need to be more or less than 20% of the bit period; however transitions times should not be left to chance.


    There are three common methods for controlling rise and fall times in digital logic:

    1. Use a logic family that is only as fast as the application requires.

    2. Put a resistor or a ferrite in series with a device's output.

    3. Put a capacitor in parallel with a device's output.

    The first choice is often the easiest and most effective option. However, the use of a resistor or ferrite gives the designer more control and is less affected by changes that occur in logic families over time. Capacitors can actually increase the amount of high-frequency current drawn by the source device and in most cases are not appropriate choices.


    Note that it is never a good idea to try to slow down or filter a single-ended signal by impeding the flow of current in the return path. For example, one should never intentionally route a low-speed trace over a gap in a return plane in an attempt to filter out the high-frequency noise.


    Ferrite beads tend to be effective in blocking noise currents in power supplies and typically have maximum values of impedance of the order of a few hundred ohms. Therefore, in order for them to be effective, they must be in series with impedances that are no larger than the bead impedance, since otherwise the bead impedance would be overshadowed by this larger impedance. The intent is to use the bead to block noise currents by adding significant impedance to the path. Circuit impedances tend to be small in power supplies as opposed to other electronic circuits. Therefore insertion of a bead tends to provide a significant increase in the circuit impedance in power supply circuits.

               The main source of radiation in digital circuits is the processor clock (or clocks) and its harmonics.

  • The narrowband emissions should be minimized first, by proper layout, grounding and buffering of clock lines.

  • Where circuit constraints allow it, is recommended to slow clock edges to minimize harmonic generation. This can be done in three ways: series impedance, parallel capacitance or by using a low-performance buffer. Generally, slugging the clock output with a parallel capacitor is undesirable because although it has the desired effect of reducing the dv/dt feeding into the clock line, it increases the capacitive loading on the driver and hence increases the di/dt drawn from its supply pins; the overall effect may be to worsen the emissions rather than improve them.

  • It is preferable to increase the series impedance of the driver output at the harmonic frequencies, and this can best be done with a small ferrite impeder in series with the output.

  • A low-value resistor is often an acceptable substitute; low-loss inductors are less helpful as they tend to introduce ringing.



    Ringing on transmission lines

    If you transmit data or clocks down long lines, these must be terminated to prevent ringing. Ringing is generated on the transitions of digital signals when a portion of the signal is reflected back down the line due to a mismatch between the line impedance and the terminating impedance. A similar mismatch at the driving end will re-reflect a further portion towards the receiver, and so on. Severe ringing will affect the data transfer, by causing spurious transitions, if it exceeds the device’s input noise margin. Aside from its effect on noise margins, ringing may also be a source of radiated interference in its own right. The amplitude of the ringing depends on the degree of mismatch at either end of the line while the frequency depends on the electrical length

    of the line. A digital driver/receiver combination should be analysed in terms of its transmission line behaviour if: 2 x tPD x line length > transition time (where tPD is the line propagation delay in ns per unit length).


    Digital circuit decoupling

    No matter how good the VCC and ground connections are, they will introduce impedance which will create switching noise from the transient switching currents taken from the VCC pins. The purpose of a decoupling capacitor is to maintain low dynamic impedance from the individual IC supply voltage to ground. This minimizes the local supply voltage droop when a fast current pulse is taken from it, and more importantly it minimizes the lengths of track which carry high di/dt currents. Placement is critical; the capacitor must be tracked close to the circuit it is decoupling.